Semiconductor devices and fabrication methods thereof

ABSTRACT

A semiconductor device includes a base substrate including an NMOS region and a PMOS region. The PMOS region includes a first P-type region and a second P-type region. The semiconductor device also includes an interlayer dielectric layer, a gate structure formed through the interlayer dielectric layer and including an N-type region gate structure formed in the NMOS region, a first gate structure formed in the first P-type region and connected to the N-type region gate structure, and a second gate structure formed in the second P-type region and connected to the first gate structure. The direction from the N-type region gate structure to the second gate structure is an extending direction of the gate structure, and along a direction perpendicular to the extending direction of the gate structure, the width of the first gate structure is larger than the width of the second gate structure.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims the priority of Chinese Patent Application No.CN201611248887.1, filed on Dec. 29, 2016, the entire content of which isincorporated herein by reference.

FIELD OF THE DISCLOSURE

The present disclosure generally relates to the field of semiconductorfabrication technology and, more particularly, relates to semiconductordevices and fabrication methods thereof.

BACKGROUND

The major semiconductor devices for integrated circuits (ICs),especially in very-large scale integrated (VLSI) circuits, includemetal-oxide-semiconductor field-effect transistors (MOSFETs). With thecontinuous development of IC manufacturing technology, the technicalnodes of semiconductor devices continue to decrease, and the geometricaldimensions of semiconductor devices become smaller and smaller followingthe Moore's law. When the reduction of the dimensions of semiconductordevices reaches a certain level, various secondary effects due toapproaching to the physical limits of semiconductor devices begin toemerge, and thus further scaling down the feature size of semiconductordevices becomes more and more difficult. Among all the problems in thefield of semiconductor manufacturing, the most challenging one is tosolve the large leakage current issue in semiconductor devices.Specifically, a large leakage current in a semiconductor device ismainly caused by the continuous decrease in the thickness of theconventional dielectric layer in the semiconductor devices.

Conventional solutions include use of a high-k material to replace thecommonly-used SiO₂ as the gate dielectric material and also use a metalmaterial as the gate electrode material to avoid Fermi level pinningbetween the high-k material and the conventional gate electrode materialand also avoid boron penetration. Such a gate structure using a high-kmaterial to form the gate dielectric layer and a metal material to formthe gate electrode is known as a high-k metal gate (HKMG). Theintroduction of the HKMG reduces the leakage current in semiconductorstructures.

Although the introduction of the HKMG may have improved the electricalperformance of semiconductor devices to a certain extent, the electricalperformance of existing semiconductor devices may still need to beimproved. The disclosed semiconductor structures and fabrication methodsthereof are directed to solve one or more problems set forth above andother problems in the art.

BRIEF SUMMARY OF THE DISCLOSURE

One aspect of the present disclosure provides a semiconductor device.The semiconductor device includes a base substrate. The base substrateincludes an N-type metal-oxide-semiconductor (NMOS) region and a P-typemetal-oxide-semiconductor (PMOS) region adjacent to the NMOS region. ThePMOS region includes a first P-type region adjacent to the NMOS regionand a second P-type region adjacent to the first P-type region. AnN-type device is formed in the NMOS region, and a P-type device isformed in the PMOS region. The semiconductor device also includes aninterlayer dielectric layer formed on the base substrate, a gatestructure formed through the interlayer dielectric layer and includingan N-type region gate structure formed on the base substrate in the NMOSregion, a first gate structure formed on the substrate in the firstP-type region and connected to the N-type region gate structure, and asecond gate structure formed on the substrate in the second P-typeregion and connected to the first gate structure. The direction from theN-type region gate structure to the second gate structure is anextending direction of the gate structure, and along a directionperpendicular to the extending direction of the gate structure, thewidth of the first gate structure is larger than the width of the secondgate structure.

Another aspect of the present disclosure provides a method forfabricating a semiconductor device. The method includes forming aninterlayer dielectric layer on a base substrate. The base substrateincludes an NMOS region and a PMOS region adjacent to the NMOS region.The PMOS region includes a first P-type region adjacent to the NMOSregion and a second P-type region adjacent to the first P-type region.The NMOS region is used to form an N-type device, and the PMOS region isused to form a P-type device. The method also includes forming an N-typeregion opening in the NMOS region through the interlayer dielectriclayer, a first opening in the first P-type region through the interlayerdielectric layer and connected to the N-type region opening, and asecond opening in the second P-type region through the interlayerdielectric layer and connected to the first P-type opening. Thedirection from the N-type region opening to the second opening is anextending direction of a subsequently-formed gate structure, and along adirection perpendicular to the extending direction of the gatestructure, the width of the first opening is larger than the width ofthe second opening.

Other aspects of the present disclosure can be understood by thoseskilled in the art in light of the description, the claims, and thedrawings of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

The following drawings are merely examples for illustrative purposesaccording to various disclosed embodiments and are not intended to limitthe scope of the present disclosure.

FIGS. 1-2 illustrate schematic structural views of a semiconductordevice;

FIGS. 3-5 illustrate schematic structural views of an exemplarysemiconductor device consistent with various embodiments of the presentdisclosure;

FIGS. 6-7 illustrate schematic views of another exemplary semiconductordevice consistent with various embodiments of the present disclosure;

FIGS. 8-13 illustrate schematic views of semiconductor structures atcertain stages of an exemplary fabrication process for forming asemiconductor device consistent with various embodiments of the presentdisclosure; and

FIG. 14 illustrates a flowchart of an exemplary method for fabricating asemiconductor device consistent with various disclosed embodiments ofthe present disclosure.

DETAILED DESCRIPTION

Reference will now be made in detail to exemplary embodiments of theinvention, which are illustrated in the accompanying drawings. Whereverpossible, the same reference numbers will be used throughout thedrawings to refer to the same or like parts.

In semiconductor devices, when the width of the gate structure of anN-type metal-oxide-semiconductor (NMOS) device and the width of the gatestructure of an adjacent P-type metal-oxide-semiconductor (PMOS) deviceare identical in the channel length direction, the response speed of thePMOS device may be slow, and thus the alternating current (AC)performance of the semiconductor device may be affected. Specifically,when the channel length of the semiconductor device continuouslydecreases, the above problem may become more and more severe.

FIGS. 1-2 illustrate schematic views of a SRAM device. FIG. 1 shows aschematic top view of the SRAM device and FIG. 2 shows an enlarged topview of the gate structure shown in FIG. 1.

Referring to FIG. 1, the SRAM device includes a pull down (PD)transistor region 11, a pass gate (PG) transistor region 12, and a pullup (PU) transistor region 13. The PD transistor region 11 and the PGtransistor region 12 are both NMOS regions. The PU transistor region 13is a PMOS region. The PD transistor region 11 and the PU transistorregion 13 are next to each other.

The SRAM device also includes a plurality of discrete fin structures 20.The PD transistor region 11 and the PG transistor region 12 share twofin structures 20. In addition, a fin structure 20 is formed entirely inthe PU transistor region 13. That is, the fin structure 20 formed in thePU transistor region 13 is separated from other regions.

The SRAM device further includes a first gate structure 21 formed acrossthe fin structure 20 in the PG transistor region 12.

Moreover, the SRAM device includes a second gate structure 22 formedacross the fin structures 20 formed in the PD transistor region 11 andalso across the fin structure 20 formed in the PU transistor region 13.The PD transistor region 11 and the PU transistor region 13 share a samesecond gate structure 22.

Referring to FIG. 2, the second gate structure 22 includes a gatedielectric layer 31 formed in the PD transistor region 11 and the PUtransistor region 13, a barrier layer 32 formed on the gate dielectriclayer 31, a P-type work function (WF) layer 33 formed on the barrierlayer 32 in the PU transistor region 13, an N-type WF layer 34 formed onthe barrier layer 32 in the PD transistor region 11 and also on theP-type WF layer 33 in the PU transistor region 13, and a gate electrodelayer 35 filling up an opening formed in the PD transistor region 11 andsurrounded by the N-type WF layer 34.

Because the number of film layers in the second gate structure 22 formedin the PU transistor region 13 is larger than the number of film layersin the second gate structure 22 formed in the PD transistor region 11,the dimension of the opening formed in the PU transistor region 13 andsurrounded by the N-type WF layer 34 is substantially smaller than thedimension of the opening formed in the PD transistor region 11 andsurrounded by the N-type WF layer 34. Specifically, the dimension of anopening surrounded by the N-type WF layer 34 refers to a measure of theopening in the length direction of the channel. Therefore, during theprocess to fill in the gate electrode layer 35, the gate electrode layer35 is easily filled into the opening formed in the PD transistor region11 and surrounded by the N-type WF layer 34. In addition, it may bedifficult to fill the gate electrode layer 35 into the opening formed inthe PU transistor region 13 and surrounded by the N-type WF layer 34.

As such, at the boundary region 10 between the PD transistor region 11and PU transistor region 13, the N-type WF layer 34 formed in the PUtransistor region may not be covered by the gate electrode layer 35, anda gap 36 may be formed in the second gate structure 22 in the PUtransistor region to expose the N-type WF layer 34. Therefore, thesecond gate structure 22 formed in the PU transistor region 13 at theboundary region 10 may have a relatively high resistance, causing a slowresponse speed of the PU transistor formed in the PU transistor region13. Therefore, the electrical performance of the SRAM device may beaffected.

Further, when the portion of the N-type WF layer 34 formed in the PUtransistor region 13 at the boundary region 10 is also covered by thegate electrode layer 35, the resistance of the second gate structure 22of the PU transistor may be reduced. Therefore, the response speed ofthe PU transistor may be improved.

The present disclosure provides a semiconductor device and fabricationmethod thereof to improve the response speed of PMOS transistors insemiconductor devices, and thus improve the electrical performance ofthe semiconductor devices.

FIGS. 3-5 illustrate schematic structural views of an exemplarysemiconductor device consistent with various embodiments of the presentdisclosure. Specifically, FIG. 3 shows a schematic top view of thesemiconductor device, FIG. 4 shows an enlarged top view of the gatestructure shown in FIG. 3, the left panel (region I) of FIG. 5 shows aschematic cross-section view of the semiconductor structure shown inFIG. 3 along an AA1 line, the center panel (region II1) of FIG. 5 showsa schematic cross-section view of the semiconductor structure shown inFIG. 3 along a BB1 line, and the right panel (region II2) of FIG. 5shows a schematic cross-section view of the semiconductor structureshown in FIG. 3 along a CC1 line.

Referring to FIGS. 3-5, the semiconductor device may include a basesubstrate and an interlayer dielectric layer 104 formed on the basesubstrate. The base substrate may include an NMOS region I and a PMOSregion II adjacent to the NMOS region I. The NMOS region I may includean N-type device and the PMOS region II may include a P-type device. ThePMOS region II may include a first P-type region II1 adjacent to theNMOS region I and a second P-type region II2 adjacent to the firstP-type region II1.

The semiconductor device may include a gate structure formed through theinterlayer dielectric layer 104. The gate structure may include anN-type region gate structure 105 formed on the base substrate in theNMOS region I, a first gate structure 106 formed on the base substratein the first P-type region II1 and connected to the N-type region gatestructure 105, a second gate structure 107 formed on the base substratein the second P-type region II2 and connected to the first gatestructure 106. The direction from the N-type region gate structure 105to the second gate structure 107 may be the extending direction 0L ofthe gate structure. Moreover, along a direction perpendicular to theextending direction 0L of the gate structure, the width W1 of the firstgate structure 106 may be larger than the width W2 of the second gatestructure 107.

The semiconductor device may also include an N-type source/drain dopedregion 108 formed in the base substrate on each side of the N-type gatestructure 105, and a P-type source/drain doped region 109 formed in thebase substrate on each side of the second gate structure 107.

In one embodiment, the gate structure may further include a gatedielectric layer 111 formed on the base substrate of the NMOS region Iand the PMOS region II and also on the sidewall surfaces of theinterlayer dielectric layer 104, a P-type WF layer 113 formed on thegate dielectric layer 111 in the first P-type region II1 and the secondP-type region II2, an N-type WF layer 114 formed on the gate dielectriclayer in the NMOS region I and also on the P-type WF layer 113, and agate electrode layer 115 formed on the N-type WF layer 114 in the NMOSregion I and also on the N-type WF layer 114 in the first P-type regionII1.

In the following, a fin field-effect transistor (Fin-FET) device isdescribed as an example to illustrate the disclosed semiconductordevice, although any suitable semiconductor devices may be formed orincluded according to various embodiments of the present disclosure. Thebase substrate may include a substrate 101 and a plurality of finstructures 102 protruding from the substrate 101. The base substrate mayalso include an isolation structure 103 formed on the substrate 101between neighboring fin structures 102. The isolation structure 103 maycover a portion of the sidewall surfaces of each fin structure 102, andthe top surface of the isolation structure 103 may be lower than the topsurfaces of the fin structures 102.

The plurality of fin structures 102 may be formed in both the NMOSregion I and the second P-type region II2. In addition, the plurality offin structures 102 may be arranged in parallel to each other.

Accordingly, the gate structure may be formed on the isolation structure103 and across the plurality of fin structures 102. The gate structuremay cover a portion of the top and sidewall surfaces of each finstructure 102. Specifically, the N-type region gate structure 105 may beformed on the isolation structure 103 of the NMOS region I and acrossthe fin structure 102 in the NMOS region I, the first gate structure 106may be formed on the isolation structure 103 of the first P-type regionII1, the second gate structure 107 may be formed on the isolationstructure 103 in the second P-type region II2 and across the finstructure 102 in the second P-type region II2.

The substrate 101 may be made of silicon, germanium, SiGe, SiC, GaAs,InAs, or any other appropriate semiconductor material. The substrate 101may also be made of silicon on insulator (SOI), germanium on insulator(GOI), or any other composite semiconductor structure. The plurality offin structures 102 may be made of silicon, germanium, SiGe, SiC, GaAs,InAs, or any other appropriate semiconductor material. In oneembodiment, the substrate 101 is made of silicon and the fin structures102 are also made of silicon.

The isolation structure 103 may be made of SiO_(x), SiN_(x), SiON, orany other appropriate material. In one embodiment, the isolationstructure 103 is made of SiO_(x).

In other embodiments, the semiconductor device may also be a planardevice, and accordingly, the base substrate may be a planar substrate.

The interlayer dielectric layer 104 may be made of SiO_(x), SiN_(x),and/or SiON. The interlayer dielectric layer 104 may also be made of alow-k dielectric material. Specifically, the low-k dielectric materialmay refer to a material with a relative dielectric constant smaller thanthe relative dielectric constant of SiO₂. In one embodiment, theinterlayer dielectric layer 104 is made of SiO_(x).

In one embodiment, the top surface of the interlayer dielectric layer104 may be leveled with the top surfaces of the gate structure. In otherembodiments, the top surface of the interlayer dielectric layer 104 maybe lower than the top surface of the gate structure.

The extending direction 0L of the gate structure may be perpendicular tothe channel length direction. In one embodiment, a direction from theN-type source/drain doped region 108 on one side of the N-type regiongate structure 105 to the N-type source/drain doped region 108 on theother side of the N-type region gate structure 105 may be perpendicularto the extending direction 0L of the gate structure. Moreover, adirection from the P-type source/drain doped region 109 on one side ofthe second gate structure 107 to the P-type source/drain doped region109 on the other side of the second gate structure 107 may beperpendicular to the extending direction 0L of the gate structure.

The N-type source/drain doped regions 108 may be used as the source andthe drain of the N-type device, and the P-type source/drain dopedregions 109 may be used as the source and the drain of the P-typedevice. In one embodiment, the N-type source/drain doped regions 108 maybe formed in the fin structure 102 on the two opposite sides of theN-type region gate structure 105, and the P-type source/drain dopedregions 109 may be formed in the fin structure on the two opposite sidesof the second gate structure 107.

In one embodiment, in a direction perpendicular to the extendingdirection of the gate structure, the width of the N-type region gatestructure 105 may remain a constant value.

In order to meet the performance requirements of the semiconductordevice, a distance between the two N-type source/drain doped regions 108on the opposite sides of the N-type region gate structure 105 may be afirst distance, a distance between the two P-type source/drain dopedregions 109 on the opposite sides of the second gate structure 107 maybe a second distance, and the second distance may be equal to the firstdistance. Therefore, in one embodiment, the width of the N-type regiongate structure 105 between the two neighboring N-type source/drain dopedregions 108 may be equal to the width of the second gate structure 107between the two neighboring P-type source/drain doped regions 109. Thatis, in one embodiment, along the direction perpendicular to theextending direction 0L of the gate structure, the width W of the N-typeregion gate structure 105 may be equal to the width W2 of the secondgate structure 107.

In one embodiment, the first gate structure 106 may be adjacent to theN-type region gate structure 105. Along the direction perpendicular tothe extending direction 0L of the gate structure, the width W2 of thesecond gate structure 107 may be actually used to control the channellength of the P-type device. In addition, along the directionperpendicular to the extending direction 0L of the gate structure, thewidth W of the N-type region gate structure 105 may be actually used tocontrol the channel length of the N-type device.

In one embodiment, the gate dielectric layer may have a multiple-layerstructure including an interfacial layer (not shown) and a high-kdielectric layer (not shown) formed on the interfacial layer. Theinterfacial layer may be made of SiO_(x) and/or SiON, and the high-kdielectric layer may be made of a high-k dielectric material. The high-kdielectric material may refer to a material with a relative dielectricconstant greater than the relative dielectric constant of SiO₂. In oneembodiment, the high-k dielectric layer is made of HfO₂. In otherembodiments, the high-k dielectric layer may be made of HfSiO, HfSiON,HfTaO, HfTiO, HfZrO, ZrO₂, or Al₂O₃.

In some other embodiments, the gate dielectric layer may also have asingle-layer structure including a high-k dielectric layer.

In one embodiment, in order to provide protection for the gatedielectric layer 111 and prevent undesired ion diffusion into the gatedielectric layer 111, the semiconductor device may also include abarrier layer 112 formed on the gate dielectric layer in the NMOS regionI, the first P-type region II1, and the second P-type region II2.Accordingly, the P-type WF layer 113 may be formed on the barrier layer112 in the first P-type region II1 and the second P-type region II2.

In one embodiment, the barrier layer 112 may be made of TiN, and thethickness of the barrier layer 112 may be in a range of approximately 5Å to 30 Å. In other embodiments, the barrier layer may be made of TaN.

The P-type WF layer 113 may be formed in the PMOS region II and may beused to adjust the threshold voltage of the P-type device formed in thePMOS region II. The P-type WF layer 113 may be made of a material with aWF value in a range of approximately 5.1 eV to 5.5 eV, such as 5.2 eV,5.3 eV, 5.4 eV, etc. The P-type WF layer 113 may be made of one or moreof Ta, TiN, TaN, TaSiN, and TiSiN. In one embodiment, the P-type WFlayer 113 is made of TiN, and the thickness of the P-type WF layer 113is in a range of approximately 10 Å to 3 Å.

Further, in order to avoid undesired effect on the threshold voltage ofthe N-type device caused by the P-type WF layer 113, the P-type WF layer113 may only be formed in the PMOS region II.

The N-type WF layer 114 may be used to adjust the threshold voltage ofthe N-type device. The N-type WF layer 114 may be made of a materialwith a WF value in a range of approximately 3.9 eV to 4.5 eV, such as4.0 eV, 4.1 eV, 4.3 eV, etc. The N-type WF layer 114 may be made of oneor more of TiAl, TiAlC, TaAlN, TiAlN, TaCN, and AlN. In one embodiment,the N-type WF layer 114 is made of TiAl, and the thickness of the N-typeWF layer 114 is in a range of approximately 20 Å to 70 Å.

The N-type WF layer 114 may have relatively small effect on thethreshold voltage of the P-type device. Therefore, in order to reducethe fabrication process for the semiconductor device, the N-type WFlayer 114 may be formed not only in the NMOS region I, but also in thePMOS region II.

Therefore, the N-type region gate structure 105 may include the gatedielectric layer 111, the barrier layer 112, and the N-type WF layer 114formed in the NMOS region I, the first gate structure 106 may includethe gate dielectric layer 111, the barrier layer 112, the P-type WFlayer 113, and the N-type WF layer 114 formed in the first P-type regionII1, and the second gate structure 107 may include the gate dielectriclayer 111, the barrier layer 112, the P-type WF layer 113, and theN-type WF layer 114 formed in the second P-type region II2.

The gate electrode layer 115 may be made of Cu, Al, W, or any otherappropriate material. The gate electrode layer 115 may be used toelectrically connect the N-type gate structure 105, the first gatestructure 106, and the second gate structure 107 to external devices orcircuits.

The first gate structure 106 together with the second gate structure 107may form the P-type region gate structure for the P-type device.

Because along the direction perpendicular to the extending direction 0Lof the gate structure, the width W2 of the second gate structure 107 isequal to the width W of the N-type region gate structure 105, the spacethat the second gate structure 107 is able to provide for the gateelectrode layer 115 may be smaller than the space that the N-type regiongate structure 105 is able to provide for the gate electrode layer 115.Therefore, the space in the second gate structure 107 occupied by thegate electrode layer 115 may be smaller than the space in the N-typeregion gate structure 105 occupied by the gate electrode layer 115.

Further, along the direction perpendicular to the extending direction 0Lof the gate structure, the width W1 of the first gate structure 106 isgreater than the width W2 of the second gate structure 107. Therefore,the space that the first gate structure 106 is able to provide for thegate electrode layer 115 may be larger than the space that the secondgate structure 107 is able to provide for the gate electrode layer 115.The gate electrode layer 115 may be able to fill the opening surroundedby the N-type WF layer 114 in the first P-type region II1. As such, thegate electrode layer 115 may be formed not only on the N-type WF layer114 in the NMOS region I, but also on the N-type WF layer 114 in thefirst P-type region II1.

In one embodiment, the top surface of the gate electrode layer 115 maybe leveled with the top surface of the N-type WF layer formed on thesidewall surfaces of the interlayer dielectric layer 104 in the NMOSregion I. That is, the gate electrode layer 115 may also be regarded asfilling up the opening formed in the NMOS region I and surrounded by theN-type WF layer 114. In one embodiment, the gate electrode layer 115 inthe NMOS region I may fill up the opening formed in the NMOS region Iand surrounded by the N-type WF layer 114. In other embodiments, thegate electrode layer formed in the NMOS region may include a gap. Thatis, the gate electrode layer may not completely fill the opening in theNMOS region.

In one embodiment, the top surface of the gate electrode layer may alsobe leveled with the top surface of the N-type WF layer formed on thesidewall surfaces of the interlayer dielectric layer 104 in the firstP-type region II1. That is, the gate electrode layer 115 may also beregarded as filling up the opening formed in the first P-type region II1and surrounded by the N-type WF layer 114. Therefore, the gate electrodelayer 115 in the first P-type region II1 may fill up the opening formedin the first P-type region II1 and surrounded by the N-type WF layer114. In other embodiments, the gate electrode layer formed in the firstP-type region II1 may include a gap. That is, the gate electrode layermay not completely fill the opening in the NMOS region.

The gate electrode layer 115 may also be formed on the N-type WF layer114 in the second P-type region II2.

In one embodiment, along the direction perpendicular to the extendingdirection 0L of the gate structure, the width W1 of the first gatestructure is larger than the width W of the N-type region gate structure105, and the width W of the N-type region gate structure 105 is equal tothe width W2 of the second gate structure 107.

Along the direction perpendicular to the extending direction 0L of thegate structure, the difference between the width W1 of the first gatestructure 106 and the width W2 of the second gate structure 107 may notbe too small or too large. When the difference between the width W1 ofthe first gate structure 106 and the width W2 of the second gatestructure 107 is too small, the space that the second gate structure 107provides for the gate electrode layer 115 may still be small, which isnot conducive to filling in the gate electrode layer 115 in the firstP-type region II1. However, when the difference between the width W1 ofthe first gate structure 106 and the width W2 of the second gatestructure 107 is too large, the space occupied by the P-type gatestructure may be overly large, which is not conducive to miniaturizationand micromation of devices.

Therefore, in one embodiment, along the direction perpendicular to theextending direction of the gate structure, the difference between thewidth W1 of the first gate structure 106 and the width W2 of the secondgate structure 107 may be in a range of approximately 1 nm to 5 nm.

Moreover, along the extending direction 0L of the gate structure, thelength L of the first gate structure 106 may not be too large or toosmall. When the length L of the first gate structure 106 is too small,the space that the first gate structure 106 provides for the gateelectrode layer 115 may be too small, which is not conducive to fillingin the gate electrode layer 115 in the first P-type region II1. However,when the length L of the first gate structure 106 is too large, thefirst gate structure may affect the channel length in the P-type device.

Therefore, in one embodiment, along the extending direction 0L of thegate structure, the length L of the first gate structure 106 may be in arange of approximately 3 nm to 5 nm.

In one embodiment, in a plane parallel to the surface of the basesubstrate, the cross section of the gate structure may have a crossshape. Specifically, the N-type region gate structure 105 and the secondgate structure 107 may together form a horizontal bar of the cross, andthe first gate structure 106 may form a vertical bar of the cross.

Because the gate electrode layer 115 is formed in the first gatestructure 106 of the P-type gate structure, the presence of the gateelectrode layer 115 may help reduce the resistance of the P-type regiongate structure. Specifically, the presence of the gate electrode layer115 in the first P-type region II1 may be conducive to reducing theresistance of the P-type region gate structure at the boundary betweenthe first P-type region II1 and the N-type region gate structure 105such that the operation speed of the P-type device may be improved andthe electrical performance of the semiconductor device may also beimproved. For example, the AC performance of the semiconductor devicemay be improved. In addition, according to the disclosed semiconductordevice, the channel length of the P-type device may still meet thedevice requirements.

The present disclosure also provides another semiconductor device. FIGS.6 and 7 show schematic cross-section views of an exemplary semiconductordevice consistent with various embodiments of the present disclosure.Specifically, FIG. 6 shows a schematic top view of the semiconductordevice. FIG. 7 shows an enlarged top view of the gate structure in thesemiconductor device shown in FIG. 6.

Referring to FIGS. 6-7, the semiconductor device may include a basesubstrate and an interlayer dielectric layer (not shown) formed on thebase substrate. The base substrate may further include an NMOS region Iand a PMOS region II adjacent to the NMOS region I. An N-type device maybe formed in the NMOS region I and a P-type device may be formed in thePMOS region II. Moreover, the PMOS region II may include a first P-typeregion II1 adjacent to the NMOS region I and a second P-type region II2adjacent to the first P-type region II1.

The semiconductor device may also include a gate structure formedthrough the interlayer dielectric layer. The gate structure may includean N-type region gate structure (not labeled) formed on the basesubstrate in the NMOS region I, a first gate structure 206 formed on thebase substrate in the first P-type region II1 and connected to theN-type region gate structure, and a second gate structure 207 formed onthe base substrate in the second P-type region II2 and connected to thefirst gate structure 206. The direction from the N-type region gatestructure to the second gate structure 207 may be the extendingdirection 0L of the gate structure. Along a direction perpendicular tothe extending direction 0L of the gate structure, the width W1 of thefirst gate structure 206 may be larger than the width W2 of the secondgate structure 207.

The semiconductor device may include an N-type source/drain doped region208 formed in the base substrate on each side of the N-type gatestructure and a P-type source/drain doped region 209 formed in the basesubstrate on each side of the P-type gate structure.

Further, the gate structure may include a gate dielectric layer 211formed on the base substrate in the NMOS region I and the PMOS region IIand also on the sidewall surfaces of the interlayer dielectric layer204, a P-type WF layer 213 formed on the gate dielectric layer 211 inthe first P-type region II1 and the second P-type region II2, an N-typeWF layer 214 formed on the gate dielectric layer 211 in the NMOS regionI and also on the P-type WF layer 213, and a gate electrode layer 215formed on the N-type WF layer 214 in the NMOS region I and also on theN-type WF layer 214 in the first P-type region II1.

In the following, a Fin-FET device is described as an example toillustrate the disclosed semiconductor device. Referring to FIGS. 6-7,the base substrate of the semiconductor device may include a substrate(not shown) and a plurality of fin structures 202 protruding from thesubstrate. The base substrate may also include an isolation structure(not shown) formed on the substrate between neighboring fin structures202.

The semiconductor device may also include a barrier layer 212 formed onthe gate dielectric layer 211 formed in the NMOS region I, the firstP-type region II1, and the second P-type region II2. Accordingly, theP-type WF layer 213 may be formed on the barrier layer 212 in the firstP-type region II1 and the second P-type region II2. The barrier layer212 may be made of TiN or TaN.

In various embodiments, the base substrate, the interlayer dielectriclayer, the N-type source/drain doped region 208, the P-type source/draindoped region 209, the gate dielectric layer 211, the barrier layer 212,the P-type WF layer 213, the N-type WF layer 214 depicted in FIGS. 6-7may be substantially the same or similar with corresponding layersdepicted in FIGS. 3-5.

In one embodiment, along the direction perpendicular to the extendingdirection 0L of the gate structure, a difference between the width W1 ofthe first gate structure 206 and the width W2 of the second gatestructure 207 may be in a range of approximately 1 nm to 5 nm. Moreover,along the extending direction 0L of the gate structure, the length L ofthe first gate structure may be in a range of approximately 3 nm to 5nm.

Different from the N-type region gate structure in embodiments describedabove, the N-type region gate structure in the present embodiment mayinclude a third gate structure 235 connected to the first gate structure206 and a fourth gate structure 245 connected to the third gatestructure 235. Accordingly, the N-type source/drain doped regions 208may be formed in the base substrate on both sides of the fourth gatestructure 245. Moreover, along the direction perpendicular to theextending direction 0L of the gate structure, the width W3 of the thirdgate structure 235 may be larger than the width W4 of the fourth gatestructure 245.

In one embodiment, along the direction perpendicular to the extendingdirection 0L of the gate structure, the width W4 of the fourth gateelectrode 245 may be equal to the width W2 of the second gate structure207. Therefore, the channel length in the N-type device may be the sameas the channel length of the P-type device such that the deviceperformance requirements are satisfied.

In one embodiment, along the direction perpendicular to the extendingdirection 0L of the gate structure, the width W3 of the third gatestructure 235 may be equal to the width W1 of the first gate structure206. As such, the method for forming the gate structure of thesemiconductor device may be simplified.

Moreover, along the extending direction 0L of the gate structure, thelength of the third gate structure 235 may not be too large or toosmall. When the length of the third gate structure 235 is too large, thethird gate structure 235 may have undesired influence on the channellength of the N-type device. However, when the length of the third gatestructure 235 is too small, the short length of the third gate structure235 may not have significant effect on improving the filling ability ofthe gate electrode layer 215 in the first gate structure 206. Therefore,in one embodiment, along the extending direction 0L of the gatestructure, the length of the third gate structure 235 is in a range ofapproximately 1 nm to 5 nm.

In one embodiment, the top surface of the gate electrode layer 215 maybe leveled with the top surface of the portion of the N-type WF layer214 formed on the sidewall surfaces of the interlayer dielectric layer204 in the NMOS region I. The top surface of the gate electrode layer215 may also be leveled with the top surface of the portion of theN-type WF layer 214 formed on the sidewall surfaces of the interlayerdielectric layer 204 in the first P-type region II1. In addition, thegate electrode layer 215 may also be formed on the portion of the N-typeWF layer 214 formed in the second P-type region II2.

The gate electrode layer 215 depicted in FIGS. 6-7 may be substantiallythe same or similar with corresponding layer depicted in FIGS. 3-5.

In one embodiment, in a plane parallel to the surface of the basesubstrate, the cross section of the gate structure may have a crossshape. Specifically, the fourth gate structure 245 and the second gatestructure 207 may together form a horizontal bar of the cross, and thethird gate structure and the first gate structure 206 may together forma vertical bar of the cross.

In one embodiment, the third gate structure 235 may be next to the firstgate structure 206. In addition, because the width W3 of the third gatestructure 235 may be greater than the width W4 of the fourth gatestructure 245, the space that the third gate structure 235 is able toprovide for the gate electrode layer 215 may be larger than the spacethat the fourth gate structure 245 is able to provide for the gateelectrode layer 215. Moreover, because the third gate structure 235 maybe next to the first gate structure 206, the gate electrode layer 215formed in the first P-type region II1 may easily fill into the firstP-type region II1 such that the filling effect of the gate electrodelayer 215 in the first gate structure 206 may be improved. Therefore,the resistance of the first gate structure 206 may be further reduced.Accordingly, the resistance of the P-type region gate structure may bereduced and the operation speed of the P-type device may be furtherimproved.

Moreover, the present disclosure also provides a method for fabricatingsemiconductor devices. FIG. 14 illustrates a flowchart of an exemplarymethod for fabricating a semiconductor device consistent with variousdisclosed embodiments in the present disclosure. FIGS. 8-13 illustrateschematic views of semiconductor structures at certain stages of thefabricating method.

Referring to FIG. 14, at the beginning of the fabrication method, a basesubstrate including an interlayer dielectric layer formed in an NMOSregion and a PMOS region may be provided, the PMOS region including afirst P-type region adjacent to the NMOS region, and a second P-typeregion adjacent to the first P-type region (S401). FIGS. 8-9 showschematic views of a corresponding semiconductor structure.Specifically, FIG. 8 shows a schematic top view of the semiconductorstructure. The left panel of FIG. 9 shows a cross-section view of thesemiconductor structure shown in FIG. 8 along an AA1 direction, themiddle panel of FIG. 9 shows a cross-section view of the semiconductorstructure shown in FIG. 8 along a BB1 direction, and the right panel ofFIG. 9 shows a cross-section view of the semiconductor structure shownin FIG. 8 along a CC1 direction. For illustration purpose, theinterlayer dielectric layer is not shown in FIG. 8.

Referring to FIGS. 8-9, a base substrate including an interlayerdielectric layer 304 formed on the base substrate may be provided. Thebase substrate may include an NMOS region I and a PMOS region IIadjacent to the NMOS region I. The NMOS region I may be used to form anN-type device and the PMOS region II may be used to form a P-typedevice. The PMOS region II may further include a first P-type region II1adjacent to the NMOS region I, and a second P-type region II2 adjacentto the first P-type region II1.

Further, returning back to FIG. 14, an N-type region opening may beformed through the interlayer dielectric layer in the NMOS region, afirst opening may be formed through the interlayer dielectric layer inthe first P-type region, and a second opening may be formed through theinterlayer dielectric layer in the second P-type region (S402). FIGS.8-9 schematically show the N-type region opening, the first opening, andthe second opening formed in the semiconductor structure.

Referring to FIGS. 8-9, an N-type region opening 305 may be formed inthe portion of the interlayer dielectric layer 304 in the NMOS region I,and a first opening 306 connected to the N-type region opening 305 maybe formed in the portion of the interlayer dielectric layer 304 in thefirst P-type region II1, and a second opening 307 connected to the firstopening 306 may be formed in the portion of the interlayer dielectriclayer 304 in the second P-type region II2. Further, a direction from theN-type region opening 305 to the second opening 307 may be the extendingdirection 0L of the gate structure. Along a direction perpendicular tothe extending direction 0L of the gate structure, the width w1 of thefirst opening 306 may be larger than the width w2 of the second opening307. In addition, along the direction perpendicular to the extendingdirection 0L of the gate structure, an N-type source/drain doped region308 may be formed in the base substrate on each side of the N-typeregion opening 305, and a P-type source/drain doped region 309 may beformed in the base substrate on each side of the second opening 307.

In one embodiment, the base substrate may include a substrate 301 and aplurality of fin structures 302 protruding from the substrate 301. Thebase substrate may also include an isolation structure 303 formed on thesubstrate 301 between neighboring fin structures 302. The isolationstructure 303 may cover a portion of the sidewall surfaces of each finstructure 302, and the top surface of the isolation structure 303 may belower than the top surfaces of the plurality of fin structures 302.

The N-type region opening 305 may provide a process basis for subsequentformation of an N-type region gate structure, the first opening 306 mayprovide a process basis for subsequent formation of a first gatestructure, and the second opening 307 may provide a process basis forsubsequent formation of a second gate structure. Moreover, the secondgate structure and the first gate structure may together form a P-typegate structure for the P-type device.

In one embodiment, when the subsequently-formed N-type region gatestructure keeps a constant width along the direction perpendicular tothe extending direction 0L of the gate structure, the N-type regionopening 305 may also keep a constant width along the directionperpendicular to the extending direction 0L of the gate structure. Inaddition, along the direction perpendicular to the extending direction0L of the gate structure, the width W of the N-type region opening 305may be equal to the width W2 of the second opening 307 so that thechannel length of the subsequently-formed N-type device may be equal tothe channel length of the subsequently-formed P-type device. Moreover,along the direction perpendicular to the extending direction 0L of thegate structure, the width W1 of the first opening 306 may be larger thanthe width W of the N-type region opening 305.

In one embodiment, along the direction perpendicular to the extendingdirection 0L of the gate structure, the difference between the width W1of the first opening 306 and the width W2 of the second opening 307 isin a range of approximately 1 nm to 5 nm. Moreover, the length of thefirst opening 306 along the direction perpendicular to the extendingdirection 0L of the gate structure is in a range of approximately 3 nmto 5 nm.

In other embodiments, the subsequently-formed N-type region gatestructure may include a third gate structure connected to the first gatestructure and a fourth gate structure connected to the third gatestructure, and the fourth gate structure may be used to define thechannel length of the N-type device. Accordingly, the N-type regionopening may include a third opening connected to the first opening and afourth opening connected to the third opening. Moreover, along thedirection perpendicular to the extending direction of the gatestructure, the width of the third opening may be larger than the widthof the fourth opening, the width of the third opening and the width ofthe first opening may be equal to each other, and the width of thefourth opening and the width of the second opening may be equal to eachother.

Returning to FIG. 14, further, N-type source/drain doped regions may beformed in the base substrate on both sides of the N-type region openingand P-type source/drain doped regions may be formed in the basesubstrate on both sides of the second opening (S403). FIGS. 8-9schematically show the N-type source/drain doped regions and the P-typesource/drain doped regions formed in the semiconductor structure.

Referring to FIGS. 8-9, in one embodiment, an N-type source/drain dopedregion 308 may be formed in the base substrate on each side of theN-type region opening 305 and a P-type source/drain doped region 309 maybe formed in the base substrate on each side of the second opening 307.

In other embodiments, the N-type region opening may include a thirdopening connected to the first opening and a fourth opening connected tothe third opening. Accordingly, the N-type source/drain doped regionsmay be formed in the base substrate on the opposite sides of the fourthopening.

The interlayer dielectric layer 304, the N-type region opening 305, thefirst opening 306, the second opening 307, the N-type source/drain dopedregion 308, and the P-type source/drain doped region 309 may be formedby any appropriate semiconductor fabrication process encompassed in thepresent disclosure.

For example, in one embodiment, the interlayer dielectric layer 304, theN-type region opening 305, the first opening 306, the second opening307, the N-type source/drain doped region 308, and the P-typesource/drain doped region 309 may be fabricated by a process includingthe following exemplary steps.

First, a dummy gate structure may be formed on the base substrate. Thedummy gate structure may include an N-type region dummy gate structureformed on the base substrate in the NMOS region I, a first dummy gatestructure formed on the base substrate in the first P-type region II1and connected to the N-type region dummy gate structure, and a seconddummy gate structure formed on the base substrate in the second P-typeregion II2 and connected to the first dummy gate structure. Thedirection from the N-type region dummy gate structure to the seconddummy gate structure may be the extending direction of the dummy gatestructure, and thus may also be the extending direction 0L of thesubsequently-formed gate structure. Moreover, along the directionperpendicular to the extending direction 0L of the dummy gate structure,the width of the first dummy gate structure may be larger than the widthof the second dummy gate structure, and the width of the first dummygate structure may be equal to the width of the second dummy gatestructure.

Further, along the direction perpendicular to the extending direction 0Lof the dummy gate structure, an N-type source/drain doped region 308 maybe formed in the base substrate on each side of the N-type region dummygate structure, and a P-type source/drain doped region 309 may be formedin the base substrate on each side of the second dummy gate structure.Further, an interlayer dielectric layer 304 may be formed on the portionof the base substrate exposed by the dummy gate structure. Theinterlayer dielectric layer 304 may expose the top surfaces of theN-type region dummy gate structure, the first dummy gate structure, andthe second dummy gate structure.

Moreover, an N-type region opening 305 may be formed by removing theN-type region gate structure, a first opening 306 may be formed byremoving the first dummy gate structure, and a second opening 307 may beformed by removing the second dummy gate structure.

In one embodiment, unless otherwise specified, subsequent fabricationprocess may be performed based on the structure illustrated in FIG. 9.

Returning back to FIG. 14, a gate dielectric layer may be formed on thebottom and sidewall surfaces of the N-type region opening, the firstopening, and the second opening (S404). FIG. 10 shows schematiccross-section views of a corresponding semiconductor structure.

Referring to FIG. 10, a gate dielectric layer 311 may be formed on thebottom and sidewall surfaces of the N-type region opening 305, the firstopening 306, and the second opening 307. The gate dielectric layer 311may also be formed on the top surface of the interlayer dielectric layer304. In a subsequent fabrication process, the portion of the gatedielectric layer 311 formed on the top surface of the interlayerdielectric layer 304 may be removed.

In one embodiment, the gate dielectric layer 311 may include aninterfacial layer (not shown) and a high-k dielectric layer (not shown)formed on the interfacial layer. Moreover, during the fabricationprocess for the gate dielectric layer 311, the gate dielectric layer 311may be formed across the fin structure 302 and may cover a portion ofthe top and the sidewall surfaces of the fin structure 302.

The interfacial layer may provide a desired interface for the high-kdielectric layer such that the quality of the high-k dielectric layermay be improved. As such, the density of interfacial states between thehigh-k dielectric layer and the fin structure 302 may be reduced,preventing undesired effects due to direct contact between the high-kdielectric layer and the fin structure 302.

The materials used to form the interfacial layer and the high-kdielectric layer may refer to the corresponding description in the aboveembodiments of the disclosed semiconductor structure.

In one embodiment, the interfacial layer may be formed by an oxidationprocess. The interfacial layer may only be formed on the exposed portionof the top and the sidewall surfaces of the fin structure 302. In otherembodiments, the interfacial layer may be formed by a depositionprocess, such as chemical vapor deposition (CVD), physical vapordeposition (PVD), atomic layer deposition (ALD), etc. Accordingly, theinterfacial layer may also be formed on the isolation structure 302.

In one embodiment, the high-k dielectric layer may be formed by an ALDprocess. In other embodiments, the high-k dielectric layer may be formedby a CVD or PVD process.

Further, after forming the gate dielectric layer 311, the fabricationprocess may also include forming a barrier layer 312 on the gatedielectric layer 311 in the NMOS region I, the first P-type region II1,and the second P-type region II2. The barrier layer 312 may provideprotection for the gate dielectric layer 311 during subsequentfabrication process. The barrier layer 312 may be made of TiN or TaN.

Further, returning to FIG. 14, a P-type work function layer may beformed on the portion of the gate dielectric layer formed in the firstopening and the second opening (S405). FIG. 11 shows schematiccross-section views of a corresponding semiconductor structure.

Referring to FIG. 11, a P-type WF layer 313 may be formed on the portionof the gate dielectric layer 311 formed in the first opening 306 and thesecond opening 307.

In one embodiment, the P-type WF layer 313 may only be formed in thePMOS region II. The P-type WF layer 313 may also be formed on the topsurface of the interlayer dielectric layer 304 in the PMOS region II.

The P-type WF layer 313 may be formed by a process including thefollowing steps. First, a P-type WF film may be formed on the barrierlayer 312 in the N-type region opening 305, the first opening 306, andthe second opening 307. The portion of the P-type WF film formed on theNMOS region I may then be removed to form the P-type WF layer 313.

In one embodiment, the P-type WF layer 313 may be formed by an ALDprocess. In other embodiments, the P-type region WF layer may be formedby a CVD or a PVD process.

Further, returning to FIG. 14, an N-type work function layer may beformed on the portion of the gate dielectric layer in the N-type regionopening and also on the P-type work function layer in the first openingand the second opening (S406). FIG. 11 shows schematic cross-sectionviews of a corresponding semiconductor structure.

Referring to FIG. 11, an N-type WF layer 314 may be formed on theportion of gate dielectric layer 311 in the N-type region opening 305and also on the P-type WF layer 313. In one embodiment, a barrier layer312 may be formed on the gate dielectric layer 311 formed in the N-typeregion opening, and accordingly, during the process to form the N-typeWF layer 314, the N-type WF layer 314 may then be formed on the portionof the barrier layer 312 in the N-type region opening 305 and also onthe P-type WF layer 313.

In one embodiment, the N-type WF layer 314 may be formed by an ALDprocess. In other embodiments, the N-type WF layer may be formed by aCVD or a PVD process.

Further, returning to FIG. 14, a gate electrode layer may be formed onthe N-type work function layer formed in the N-type region opening andalso on the N-type work function layer formed in the first opening(S407). FIGS. 12-13 show schematic views of a correspondingsemiconductor structure. Specifically, FIG. 12 illustrates an enlargedtop view of the gate structure. FIG. 13 shows cross-section views of thesemiconductor structure developed from the structure shown in FIG. 11.

Referring to FIGS. 12-13, a gate electrode layer 315 may be formed onthe portion of the N-type WF layer 314 in the N-type region opening 305(referring to FIG. 11). Moreover, the gate electrode layer 315 may alsobe formed on the portion of the N-type WF layer 314 formed in the N-typeregion opening 305 (referring to FIG. 11). The gate electrode layer 315may be made of Cu, Al, or W.

The gate electrode layer 315 may be formed by a process including thefollowing steps. First, a gate electrode film may be formed to fill upthe N-type region opening 305, the first opening 306, and the secondopening 307. The top surface of the gate electrode film may be higherthan the top surface of the interlayer dielectric layer 304. Further,the gate electrode layer 315 may then be formed by removing the portionof the gate electrode film formed above the top surface of theinterlayer dielectric layer 304 through polishing. During the process toremove the portion of the gate electrode film formed above the topsurface of the interlayer dielectric layer 304, the portion of theN-type WF layer 314, the P-type WF layer 313, the barrier layer 312, andthe gate dielectric layer 311 formed above the top surface of theinterlayer dielectric layer 304 may also be removed.

The gate dielectric layer 311, the barrier layer 312, the P-type WFlayer 313, the N-type WF layer 314, and the gate electrode layer 315 maytogether form a gate structure. Specifically, the portion of the gatestructure formed in the NMOS region I may become an N-type region gatestructure, the portion of the gate structure formed in the first P-typeregion II1 may become the first gate structure, and the portion of thegate structure formed in the second P-type region II2 may become thesecond gate structure. Further, along the direction perpendicular to theextending direction 0L of the gate structure, the width of the firstgate structure may be larger than the width of the second gatestructure.

In one embodiment, along the direction perpendicular to the extendingdirection 0L of the gate structure, the width of the N-type region gatestructure may be equal to the width of the second gate structure.Accordingly, the width of the first gate structure may also be largerthan the width of N-type region gate structure.

In one embodiment, prior to forming the gate electrode layer 315, thenumber of film layers formed in the N-type region opening 305 may besmaller than the number of film layers formed in the second opening 307.Therefore, the space reserved for forming the gate electrode layer 315in the N-type region opening 305 may be larger than the space reservedfor forming the gate electrode layer 315 in the second opening 307 suchthat the gate electrode layer 315 may be easily fill up the N-typeregion opening 305. As such, the top surface of the gate electrode layer315 may be leveled with the top surface of the N-type WF layer 314formed on the sidewall surfaces of the N-type region opening 305.Because the space reserved for forming the gate electrode layer 315 inthe second opening 307 may be relatively small, it may be more difficultfor the gate electrode layer 315 to fill up the second opening 307. Thatis, the gate electrode layer 315 may not be easily filled into thesecond opening 307.

Prior to forming the gate electrode layer 315, the number of film layersformed in the first opening 306 may be the same as the number of filmlayers formed in the second opening 307. Therefore, along the directionperpendicular to the extending direction 0L of the gate structure, thewidth of the first opening may be larger than the width of the secondopening such that filling the gate electrode layer 315 into the firstopening 306 may be relatively easy. Therefore, the gate electrode layer315 may be formed on the N-type WF layer 314 in the first P-type regionII1, and thus the resistance of the first gate structure may be reducedand the operation speed of the P-type device may be improved.

In one embodiment, the gate electrode layer 315 may fill up the firstopening 306. In other embodiments, the gate electrode layer formed inthe first P-type region may include a gap.

In one embodiment, the gate electrode layer 315 may also be formed onthe portion of the N-type WF layer 314 formed in the second P-typeregion II2.

Moreover, along the direction perpendicular to the extending direction0L of the gate structure, the width of the second opening 307 may beequal to the width of the N-type region opening 305. Therefore, thechannel length in the formed N-type device may be the same as thechannel length in the formed P-type device such that the deviceperformance requirements may be satisfied.

In other embodiments, the N-type region opening may include a thirdopening connected to the first opening and a fourth opening connected tothe third opening. Along the direction perpendicular to the extendingdirection of the gate structure, the width of the third opening may belarger than the width of the fourth opening. Because the third openingis next to the first opening, the process difficulty in filling thefirst opening with the gate electrode layer may be further reduced,ensuring the gate electrode layer filling up the first opening.Therefore, the operation speed of the formed P-type device may befurther improved. Moreover, corresponding to the N-type region openingincluding the third opening and the fourth opening, the N-type regiongate structure may include a third gate structure connected to the firstgate structure and a fourth gate structure connected to the third gatestructure. The N-type source/drain doped regions may thus be formed inthe base substrate on both sides of the fourth opening. Along thedirection perpendicular to the extending direction of the gatestructure, the width of the third gate structure may be larger than thewidth of the fourth gate structure, the width of the fourth gatestructure may be equal to the width of the second gate structure, andthe width of the third gate structure may be equal to the width of thefirst gate structure.

Compared to conventional fabrication methods and semiconductor devices,the disclosed fabrication methods and semiconductor devices maydemonstrate several advantages.

According to the disclosed fabrication methods and semiconductordevices, an NMOS region including an N-type device may be adjacent to aPMOS region including a P-type device. The PMOS region may furtherinclude a first P-type region and a second P-type region next to thefirst P-type region. The first P-type region of the PMOS region may beadjacent to the NMOS region and the second P-type region of the PMOSregion may be adjacent to the first P-type region. An N-type region gatestructure may be formed on the base substrate in the NMOS region, afirst gate structure may be formed on the base substrate in the firstP-type region and connected to the N-type region gate structure, and asecond gate structure may be formed on the base substrate in the secondP-type region and connected to the first gate structure. Further, alongthe direction perpendicular to the extending direction of the gatestructure, the width of the first gate structure may be larger than thewidth of the second gate structure. In addition, the width of the secondgate structure may define the channel length of the P-type device.

According to the disclosed fabrication methods and semiconductordevices, the gate structure may include a gate dielectric layer, aP-type WF layer formed in both the first P-type region and the secondP-type region, an N-type WF layer formed on the portion of the gatedielectric layer in the NMOS region and also on the P-type WF layer, anda gate electrode layer formed on the portion of the N-type WF layerformed in the NMOS region and the first P-type region. Moreover, alongthe direction perpendicular to the extending direction of the gatestructure, the width of the first gate structure may be larger than thewidth of the second gate structure. Therefore, the space reserved forforming the gate electrode layer in the first gate structure may belarger than the space reserved for forming the gate electrode layer inthe second gate structure such that the gate electrode layer may be ableto fill onto the N-type WF layer in the first P-type region. Therefore,the resistance of the P-type region gate structure next to the N-typegate structure may be reduced. As such, the response speed of the P-typedevice may be improved, and the electrical performance of thesemiconductor device may be improved.

In one embodiment, along the direction perpendicular to the extendingdirection of the gate structure, the width of the N-type region gatestructure may be equal to the width of the second gate structure.Further, the N-type region gate structure may be used to define thechannel length of the N-type device. Therefore, the channel length inthe formed N-type device may be the same as the channel length in theformed P-type device such that the device performance requirements maybe satisfied.

In one embodiment, the N-type region gate structure may include a thirdgate structure connected to the first gate structure and a fourth gatestructure connected to the third gate structure. Accordingly, the N-typesource/drain doped regions may be formed in the base substrate on bothsides of the fourth opening. Specifically, along the directionperpendicular to the extending direction of the gate structure, thewidth of the third gate structure is larger than the width of the fourthgate structure. Because the third gate structure is next to the firstgate structure and the width of the third gate structure may berelatively large, the ability of filling the gate electrode layer ontothe N-type WF layer in the first P-type region may be further improved.As such, the resistance of the P-type region gate structure in theP-type device may be further reduced, and the response speed of theP-type device may be improved.

The above detailed descriptions only illustrate certain exemplaryembodiments of the present invention, and are not intended to limit thescope of the present invention. Those skilled in the art can understandthe specification as whole and technical features in the variousembodiments can be combined into other embodiments understandable tothose persons of ordinary skill in the art. Any equivalent ormodification thereof, without departing from the spirit and principle ofthe present invention, falls within the true scope of the presentinvention.

What is claimed is:
 1. A semiconductor device, comprising: a basesubstrate, including an N-type metal-oxide-semiconductor (NMOS) regionand a P-type metal-oxide-semiconductor (PMOS) region adjacent to theNMOS region, wherein the PMOS region includes a first P-type regionadjacent to the NMOS region and a second P-type region adjacent to thefirst P-type region, an N-type device is formed in the NMOS region, anda P-type device is formed in the PMOS region; an interlayer dielectriclayer formed on the base substrate; and a gate structure formed throughthe interlayer dielectric layer and including an N-type region gatestructure formed on the base substrate in the NMOS region, a first gatestructure formed on the substrate in the first P-type region andconnected to the N-type region gate structure, and a second gatestructure formed on the substrate in the second P-type region andconnected to the first gate structure, the N-type region gate structurebeing directly connected with the second gate structure through thefirst gate structure, wherein: a direction from the N-type region gatestructure to the second gate structure is an extending direction of thegate structure, along a direction perpendicular to the extendingdirection of the gate structure, a width of the first gate structure islarger than a width of the second gate structure, the N-type region gatestructure includes a third gate structure connected to the first gatestructure, and a fourth gate structure connected to the third gatestructure, and along the direction perpendicular to the extendingdirection of the gate structure, a width of the third gate structure islarger than a width of the fourth gate structure and the width of thefourth gate structure is equal to the width of the second gatestructure.
 2. The semiconductor device according to claim 1, furtherincluding: N-type source/drain doped regions formed in the basesubstrate on two opposite sides of the N-type gate structure; and P-typesource/drain doped regions formed in the base substrate on two oppositesides of the second gate structure.
 3. The semiconductor deviceaccording to claim 1, wherein the gate structure includes: a gatedielectric layer formed on the base substrate in the NMOS region and thePMOS region and also on sidewall surfaces of the interlayer dielectriclayer; a P-type work function layer formed on the gate dielectric layerin the first P-type region and the second P-type region; an N-type workfunction layer formed on the gate dielectric layer in the NMOS regionand also on the P-type work function layer; and a gate electrode layerformed on the N-type work function layer in the NMOS region and thefirst P-type region.
 4. The semiconductor device according to claim 3,wherein: a top surface of the gate electrode layer is leveled with a topsurface of the N-type work function layer formed on the sidewallsurfaces of the interlayer dielectric layer in the NMOS region.
 5. Thesemiconductor device according to claim 4, wherein: the top surface ofthe gate electrode layer is also leveled with a top surface of theN-type work function layer formed on the sidewall surfaces of theinterlayer dielectric layer in the first P-type region.
 6. Thesemiconductor device according to claim 1, wherein: along the directionperpendicular to the extending direction of the gate structure, thewidth of the first gate structure is larger than a width of the N-typeregion gate structure; and along the direction perpendicular to theextending direction of the gate structure, the width of the N-typeregion gate structure is equal to the width of the second gatestructure.
 7. The semiconductor device according to claim 1, wherein:along the direction perpendicular to the extending direction of the gatestructure, a difference between the width of the first gate structureand the width of the second gate structure is in a range ofapproximately 1 nm to 5 nm.
 8. The semiconductor device according toclaim 1, wherein: along the direction perpendicular to the extendingdirection of the gate structure, the width of the first gate structureis in a range of approximately 3 nm to 5 nm.
 9. The semiconductor deviceaccording to claim 1, wherein: the N-type source/drain doped regions areformed in the base substrate on both sides of the fourth gate structure.10. The semiconductor device according to claim 9, wherein: along thedirection perpendicular to the extending direction of the gatestructure, the width of the third gate structure is equal to the widthof the first gate structure.
 11. The semiconductor device according toclaim 2, further including: a barrier layer formed on the gatedielectric layer in the NMOS region, the first P-type region, and thesecond P-type region; and the barrier layer is made of TiN or TaN,wherein: the P-type work function layer is formed on the barrier layerin the first P-type region and the second P-type region.
 12. Thesemiconductor device according to claim 1, wherein: along a directionparallel to a surface of the base substrate, a cross section of the gatestructure has a cross shape.
 13. The semiconductor device according toclaim 1, wherein: the base substrate includes a substrate and aplurality of fin structures protruding from the substrate.
 14. Thesemiconductor device according to claim 1, wherein: a top surface of theinterlayer dielectric layer is lower than the top surface of the gatestructure.
 15. The semiconductor device according to claim 11, wherein:the N-type work function layer is directly sandwiched by the barrierlayer and the gate electrode layer in the NMOS region.
 16. Thesemiconductor device according to claim 11, wherein: the P-type workfunction layer is directly sandwiched by the N-type work function layerand the gate electrode layer in the PMOS region.